**1. Introduction**

The clock dependency can be described based on the following figure.

Starting from a data frame transferred on the bus. A desired baudrate tells how many bits are sent on the network per second. The Nominal Bit Rate (baudrate) is uniform throughout the network and is given by:

**baudrate = 1 / t**

_{NBT }**(1)**

The

**t**represents a period of the

_{NBT}**Nominal Bit Time**(NBT), i.e. single bit transfered on the bus. The NBT is separated into four non-overlaping segments, SYNC_SEG, PROP_SEG, PHASE_SEG1 and PHASE_SEG2. Each of these segments is an integer multiple of

**Time Quantum**(

**t**.

_{Q})**t**

_{NBT}= t_{Q}+PROP_SEG* t_{Q}+ PHASE_SEG1* t_{Q}+ PHASE_SEG2* t_{Q}= NBT * t_{Q}**(2)**

The below table summarizes the possible values each segment can be set to.

Note: The function MAX( , ) returns the larger of the two arguments.

The duration of the segment PHASE_SEG1 may be between 1 and 8 Time Quanta if one sample per bit is selected and may be between 2 and 8 Time Quanta if three samples per bit are selected. If three samples per bit are chosen, the most frequently sampled value is taken as the bit value.

The duration of segment PHASE_SEG2 must be equal to PHASE_SEG1, unless PHASE_SEG1 is less than the

**Information Processing Time (IPT)**, in which case PHASE_SEG2 must be equal to the Information Processing Time.

**The Information Processing Time is equal to 2 Time Quanta**

From the table, it would appear that the minimum number of Time Quanta per bit (NBT ) is 5. However, many CAN controllers require a minimum of 8 Time Quanta per bit. The maximum number of Time Quanta per bit is 25.

A Time Quantum is the atomic unit of time handled by the CAN engine and it is given by the Serial Clock (Sclock) period as

t

_{Q}= 1/Sclock = 1/[CPI_clock /(PRESDIV+1)].

**(3)**

**The CPI_clock is the CAN Protocol Interface clock**, can be either the peripheral clock (driven by the FMPLL) or the crystal oscillator clock. The PRESDIV controls a Prescaler that generates the Serial Clock (Sclock)

The clock source selection is done by the CLK_SRC bit of the CTRL register. Moreover this

register contains other fields used to control bit timing parameters as was mentioned above: PRESDIV, PROPSEG, PSEG1, PSEG2 and RJW. The SMP specifies if one or three samples per bit is used.

These parameters have to be properly calculated/selected to meet the CAN specification.

The following chapter provides a step-by-step guide for determining the optimum bit timing parameters which satisfy the requirements for proper bit sampling. Besides the desired baudrate and selected CPI clock a physical interface parameters and bus length is also needed to determine propagation segment duration.

**2 Step-by-step guide**

**STEP 1**:

**Determine minimum permissible time for the PROP_SEG segment**

Obtain the maximum propagation delay of the physical interface for both the transmitter and the receiver from the manufacturers data sheet. Calculate the propagation delay of the bus by multiplying the maximum length of the bus by the signal propagation delay of the bus cable. Use these values to calculate t

_{PROP_SEG}using equation

**t**

_{PROP_SEG}= 2(t_{BUS}+ t_{TX}+ t_{RX})**(4)**

**STEP 2**:

**Choose CPI_clock, the Prescaler and NBT**

Determine Prescaler and a Nominal Bit Time (NBT ). Basically you can

**combine equations (1), (2) and (3) into**

**NBT * Prescaler = CPI_clock / baud rate**

**(5)**

As already mentioned NBT may be integer number in range 8 to 25 and Prescaler in range 1 to 256. Find those combinations of NBT * Prescaler which is equal to CPI_clock /baud rate. There may be a lot of possible combinations. If none can be found choose different CPI_clock.

**STEP 3**:

**Calculate PROP_SEG duration**

The number of time quanta required for the PROP_SEG segment are calculated based on chosen Prescaler value

**PROP_SEG = ROUND_UP(t**

_{PROP_SEG}/ t_{Q}) =ROUND_UP(t_{PROP_SEG}*CPI_clock/Prescaler)**(6)**

where the function ROUND_UP( ) returns the argument rounded up to the next integer value.

**STEP 4**:

**Determine PHASE_SEG1, PHASE_SEG2**

From the number of Time Quanta per bit obtained in Step 2, subtract the PROP_SEG value calculated in Step 3 and subtract 1 t

_{Q}for SYNC_SEG.

**If the remaining number is an odd number greater than 3 then add one to the PROP_SEG value and recalculate.**

**If the remaining number is equal to 3 then PHASE_SEG1 = 1 and PHASE_SEG2 = 2 and only one sample per bit may be chosen. Otherwise divide the remaining number by two and assign the result to PHASE_SEG1 and PHASE_SEG2.**

**STEP 5**:

**Determine RJW**

**RJW is chosen as the smaller of 4 and PHASE_SEG1**

**STEP 6**:

**Calculate required oscillator tolerance**

There are two clock tolerance requirements which must be satisfied.

**( 2 * Δf) * 10 * t**

_{NBT}t_{RJW}**(8)**

**( 2 * Δf) * (13 * t**

_{NBT}– t_{PHASE_SEG2}) MIN(t_{PHASE_SEG1}, t_{PHASE_SEG2})**(9)**

where the function MIN( , ) returns the smaller of the two arguments. (Δf :tolerance need to be calculated)

As

**the required oscillator tollerance select the smaller of the calculated values**.

**3 Example**

Calculate the bit segments for the following system constraints:

• Bit rate = 500k bit per second

• Bus length = 10m

• Bus propagation delay = 5 x 10

^{-9}(s/m)

• Physical Interface (PCA82C250) transmitter plus receiver propagation delay = 150ns at 85 °C

• CPI_clock = 40 MHz

**STEP 1**:

Physical delay of bus = 10m x 5 ns/m = 50 (ns)

t

_{PROP_SEG}= 2(50 + 150) = 400 (ns)

**STEP 2**:

NBT * Prescaler = CPI_clock /baud rate = 40 MHz / 500kbps = 80

There can be 4 possibilities:

NBT = 20, Prescaler = 4

NBT = 16, Prescaler = 5

NBT = 10, Prescaler = 8

NBT = 8, Prescaler = 10

Lets choose the first one

**STEP 3**:

PROP_SEG = ROUND_UP(400ns * 40MHz / 4) = 4

**STEP 4**:

NBT – 1 – PROP_SEG = 20 – 1 – 4 = 15

As the result is odd increase PROP_SEG and recalculate

20 – 1 – 5 = 14

Divide the number by two and assign the result to PHASE_SEG1 and PHASE_SEG2.

PHASE_SEG1 = 7 and PHASE_SEG2 = 7

**STEP 5**:

RJW is chosen as the smaller of 4 and PHASE_SEG1, so RJW = 4

**STEP 6**:

( 2 * Δf) * 10 * t

_{NBT}t

_{RJW}

( 2 * Δf) * 10 * 20 f 0.01 = 1% (t

_{NBT}=NBT*t

_{Q};

_{ tRJW}=t

_{RJW}*t

_{Q}, So

_{ }tQ

_{ })

( 2 * Δf) * (13 * t

_{NBT}– t

_{PHASE_SEG2}) MIN(t

_{PHASE_SEG1}, t

_{PHASE_SEG2})

( 2 * Δf) * (13 * 20 – 7) Δf 0.0138 = 1.38%

required oscillator tollerance is 1%

In summary:

Prescaler = 4

Nominal Bit Time = 20

PROP_SEG = 5

PHASE_SEG1 = 7

PHASE_SEG2 = 7

RJW = 4

Oscillator tolerance = 1%

Similarly repeate steps 3-6 for next NBT, Prescaler values given in step 2.

Calculated bit timing parameters are given in following table.